Certificate in Hands-On FPGA DSP: Arduino to Vivado

Physics Department

Hands-On FPGA DSP: Arduino to Vivado

Key Feature

Code PX212

Subjects 8

Duration 8 weeks

Registration Opening 1st December 2025

Teaching Distance learning

Credits 1 ECTS-aligned (Pro&Plus)

Tuition Fees* Core €249 – Plus €349 – Pro €499

* Core = self-paced; Plus = graded capstone + 1 ECTS-aligned cert; Pro = Plus + live Q&A. Hardware not included. 12-month access. 14-day refund (under 20% progress).

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Overview
This professional certificate takes learners from Arduino-level familiarity to a working FPGA signal-processing pipeline in Xilinx Vivado. You will implement DDS → Framing (TLAST) → FFT → Burst → FIFO (64→8) → UART, stream results to your laptop, and reconstruct spectra in Python. The program blends just-in-time theory (sampling, FFT, fixed-point, streaming handshakes) with guided labs (simulation, constraints, bitstream, hardware debug). The capstone delivers a reproducible demo and a concise technical report.

Objectives

Build and explain an end-to-end 2048-point FFT pipeline on Basys-3.
Use AXI-Stream correctly (tvalid, tready, tlast) and maintain frame integrity.
Configure DDS (tuning words) and FFT IP; interpret 64-bit complex outputs.
Buffer/rate-match with FIFO (64→8) and stream ASCII-hex via UART.
Parse hex → complex in Python and plot magnitude/phase vs frequency.
Produce portfolio artifacts: bitstream, terminal capture, Python notebook, report.

Learning outcomes
You will be able to:

Explain bits, bytes, hex, two’s complement, Q-formats (Q1.15/Q1.31).
Compute sampling rate, FFT bin width Δf = F_s/N, and DDS tuning words.
Use AXI-Stream (tvalid/tready/tlast) and frame 2048-sample blocks.
Configure DDS (NCO) and XFFT IP; interpret 64-bit {Im,Re} outputs.
Gate frames with a burst FSM, buffer with a FIFO (64→8), stream via UART.
Parse 16-hex/FFT-sample to complex numbers; compute |X|, ∠, and bin index in Python.
Simulate, constrain, program, and debug the whole pipeline on hardware.

From Arduino to FPGA – Install tools, program the board, verify UART/LED.
Numbers that mean something – bits, bytes, hex, two’s-complement, Q-formats.
Sampling without surprises – F_s, frames N, Δf, coherent sampling, leakage.
Clean data in, smart data out – AXI-Stream tvalid/tready/tlast; frame 2048 samples.
Fast math on hardware – DDS tuning, FFT configuration; read 64-bit complex bins.
Make it travel – Burst gating; FIFO 64→8; UART at 115200 (CLKS_PER_BIT = f_clk/115200).
See it on screen – Python parsing: hex → {Im,Re} (signed 32) → |X|, ∠, bin → spectrum plot.
Debug & present – common pitfalls, optional ILA; finalize demo & documentation.
Capstone: Real-Time 2048-Point FFT over UART — working demo + 2,000-word technical report.

Entry Requirements

Maths: basic linear algebra, complex numbers, trigonometry; first-year signals ideas (sampling, frequency) helpful but not required.
Programming: beginner-level in Python/Arduino (variables, arrays, simple scripts).
Hardware (not included): Basys-3 (Artix-7 XC7A35T) board, micro-USB cable, and either
- a USB-to-TTL 3.3 V UART dongle to PMOD JA1 (o_Tx_Serial) + GND, or
- use the board’s on-board USB-UART with our alternate XDC notes.
Software (free): Xilinx Vivado 2019+, PuTTY (or similar), Python (Anaconda/Miniconda recommended): Python 3.10+ with numpy, matplotlib.
Computer/OS: Windows 10/11 or Ubuntu 20.04+/22.04+ (macOS via VM); admin rights to install drivers.
Time commitment: ~2–3 hours/week for 7 weeks (≈28–30 hours total, 1 ECTS-aligned).
English: good writing and communication skills in English.